This paper proposes a new architecture for multibit complex bandpass ΔΣAD modulators with built-in Switched-Capacitor (SC) circuits for application to Low-IF receivers such as used for Bluetooth and WLAN. In the realization of complex bandpass ΔΣAD modulators, we face the following problems: (i) SNR of AD converter is deteriorated by mismatches between internal analog I and Q paths. (ii) Layout design becomes complicated because of signal lines crossing by complex filter and feedback from DAC for I and Q paths in the complex modulator, and this increases required chip area. We propose a new structure for a complex bandpass ΔΣAD modulator which can be completely divided into two paths without layout crossing, and solves the problems mentioned above. The two parts of signal paths and circuits in the modulator are changed for I and Q while CLK is changed for High/Low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain timing, and they are switched by multiplexers to those used for Q and I paths at another timing. Therefore the influence from mismatches between I and Q paths is reduced by dynamic matching. As a result, the modulator is divided into two separate parts without crossing signal lines between I and Q paths and its layout design can be greatly simplified compared with conventional modulators. We have conducted MATLAB simulations to confirm the effectiveness of the proposed structure.

We demonstrated 1-Tb/s-class transmissions of field-deployed large-core low-loss fiber links, which is compliant with ITU-T G.654.E, using our newly developed real-time transponder consisting of a state-of-the-art 16-nm complementary metal-oxide-semiconductor (CMOS) based digital signal processing application-specific integrated circuit (DSP-ASIC) and an indium phosphide (InP) based high-bandwidth coherent driver modulator (HB-CDM). In this field experiment, we have achieved record transmission distances of 1122km for net data-rate 1-Tb/s transmission with dual polarization-division multiplexed (PDM) 32 quadrature amplitude modulation (QAM) signals, and of 336.6 km for net data-rate 1.2-Tb/s transmission with dual PDM-64QAM signals. This is the first demonstration of applying hybrid erbium-doped fiber amplifier (EDFA) and backward-distributed Raman amplifier were applied to terrestrial G.654.E fiber links. We also confirmed the stability of signal performance over field fiber transmission in wavelength division multiplexed (WDM) condition. The Q-factor fluctuations respectively were only less than or equal to 0.052dB and 0.07dB for PDM-32QAM and PDM-64QAM signals within continuous measurements for 60 minutes.

In general, since the in-band noise of phase-locked loops (PLLs) is mainly caused by charge pumps (CPs), large-size transistors that occupy a large area are used to improve in-band noise of CPs. With the high demand for low phase noise in recent high-performance communication systems, the issue of the trade-off between occupied area and noise in conventional CPs has become significant. A noise-canceling CP circuit is presented in this paper to mitigate the trade-off between occupied area and noise. The proposed CP can achieve lower noise performance than conventional CPs by performing additional noise cancelation. According to the simulation results, the proposed CP can reduce the current noise to 57% with the same occupied area, or can reduce the occupied area to 22% compared with that of the conventional CPs at the same noise performance. We fabricated a prototype of the proposed CP embedded in a 28-GHz LC-PLL using a 16-nm FinFET process, and 1.2-dB improvement in single sideband integrated phase noise is achieved.

Over 100 Gbit/s/ch high-speed optical transmission is required to achieve the high capacity networks that can meet future demands. The coherent receiver, which is expected to yield high frequency utilization, is a promising means of achieving such high-speed transmission. However, it requires a high-speed Analog to Digital Converter (ADC) because the received signal bandwidth would be over several tens or hundreds of GHz. To solve this problem, we propose a band-divided receiver structure for wideband optical signals. In the receiver, received wideband signals are divided into a number of narrow band signals without any guard band. We develop a band-divided receiver prototype and evaluate it in an experiment. In addition, we develop a real-time OFDM demodulator on an FPGA board that implements 1.5 GS/s ADCs. We demonstrate that the band-divided receiver prototype with its real-time OFDM demodulator and 1.5 GS/s ADC can demodulate single polarization 12 Gbit/s OFDM signals in real-time.